Design issues and performance limitations of a clock jitter insensitive multibit DAC architecture for high-performance low-power CT ΣΔ modulators

2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512) (2024) - Comments
doi: 10.1109/iscas.2004.1328385

F. Gerfers, M. Ortmanns, Y. Manoli