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P. Ciao, G. Colavolpe, L. Fanucci
Search publications for: doi:10.1109/DSD.2004.1333274 1 result
A parallel VLSI architecture for 1-Gb/s, 2048-b, rate-1/2 turbo Gallager code decoder
P. Ciao, G. Colavolpe, L. Fanucci